1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device which can efficiently remove noise due to signal reflection.
2. Description of the Related Art
A semiconductor memory device such as a dynamic random access memory (DRAM) includes an output driver for driving data generated within the memory to another device external to the memory.
FIG. 1 illustrates an output driver of a memory device. As shown in FIG. 1, the output driver includes an inverter 1, a NAND gate 2, a NOR gate 3, a PMOS transistor MP, and an NMOS transistor MN.
The PMOS transistor MP is connected to a power supply voltage VDD and the NMOS transistor MN is connected to a ground voltage VSS. In addition, the PMOS transistor MP and the NMOS transistor MN are connected to each other, and a node a between the PMOS transistor MP and the NMOS transistor MN is connected to an output terminal 4.
The output driver is generally enabled in response to an enable signal OEB having a low level and supplies sourcing current to a load capacitor (not shown) of the output terminal 4 through the PMOS transistor MP used as a pull-up transistor to charge the load capacitor when an input data D is high. In addition, when the input data D is low, the output driver supplies sinking current to the load capacitor to discharge the load capacitor of the output terminal 4 through the NMOS transistor MN used as a pull-down transistor, thereby lowering the potential of the output terminal 4.
When a semiconductor memory device is operated at higher speed, noise in an interface between a memory controller and a memory core module reduces a timing margin and therefore needs to be minimized. In a dual-rank or a multi-rank DRAM, there are more parasitic components and there are more noise as compared with a single-rank DRAM.
Another source of noise is signal reflection due to impedance mismatch. When the signal reflection is large, the inter-symbol interference (ISI) degrades the integrity of the data output signal.
In order to prevent this phenomenon, the data output signal is pre-emphasized. U.S. Pat. No. 6,759,868 and Japanese Unexamined Application Publication No. 2002-094365 disclose an output driver having a pre-emphasis function.
FIG. 2 illustrates a conventional semiconductor memory device including a pre-emphasis function. As shown in FIG. 2, the conventional semiconductor memory device includes a primary output driver having a first PMOS transistor MP1 and a first NMOS transistor MN1. In addition, the conventional semiconductor memory device further includes a secondary output driver for performing a pre-emphasis operation on a data signal output from the primary output driver. The secondary output driver includes a second PMOS transistor MP2 and a second NMOS transistor MN2.
The primary output driver and the secondary output driver are connected to a transmission line L through an output terminal and output a data signal. One end of the transmission line L may be connected to one side of a termination resistor RT. The other end of the resistor RT is electrically connected to a power supply voltage VDD.
Signal waveforms shown in FIG. 2 represent control signals applied for driving the primary output driver and the secondary output driver. The PMOS transistors MP1 and MP2 of the primary output driver and the secondary output driver are turned on by a control signal having a low level and the NMOS transistors MN1 and MN2 thereof are turned on by a control signal having a high level.
The pre-emphasis operation is performed by turning on the PMOS transistor MP2 or the NMOS transistor MN2 of the secondary output driver for a short time when the PMOS transistor MP1 or the NMOS transistor MN1 of the primary output driver is turned on. Since the pre-emphasis operation is performed to increase the voltage level of the data output signal, it better compensates the signal when it is attenuated due to the signal reflection phenomenon and reduces errors from being generated when the signal is restored.
The pre-emphasis operation is performed on the data signals having a low level and a high level. However, when the semiconductor memory device outputs the data signal, skew may be present when the data signal transitions between the low level and the high level due to a difference between components.
However, in the conventional device, the pre-emphasis operation is performed when the primary output driver is turned on, but not when the signal reflection phenomenon is occurring. If the pre-emphasis operation is not performed when the signal is reflected and attenuated in a transmission line, an attenuated signal cannot be adequately compensated. With the signal reflection, an aperture window is reduced and a safe timing margin with which to reliably operate is reduced.